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CPU architecture in which there are no asynchronous interrupts, only hardware tasks that can be suspended waiting for an external event

Poll (single choice)
yes
12 votes 66.7%
no
6 votes 33.3%
better idea:
0 votes 0.0%
18 votes total · 18 voters Poll ended

@zwol

I also like this but voted no. Cambridge had a research architecture like this and I really liked it when I first saw it: architecturally, you have an unbounded (bounded by memory) set of hyperthreads. Microarchitecturally, you have a finite number and all runnable threads are pulled in when they can be. You can build a system with no register rename or speculation if you do this, which means it can get enormous (GPU-like) aggregate throughput.

The problems come when you want to provide scheduling policies. Think about how you’d implement a priority-inheriting mutex on such a system and you realise quite how complex a hardware-software interface you need. I’m willing to believe it’s possible but it’s a multi-year well-funded prototype to come up with something that actually addresses the hard problems.

@david_chisnall I have the impression Spring's solution rests on "doors" being synchronous. If I designed a microkernel it would be strictly asynchronous: all cross-domain invocations "just" queue a message and the *only* blocking operation is "wait for next message". Backpressure is achieved by charging senders for all messages in flight. I *think* this environment could handle priority inheritance by tracking the task priorities of all unacknowledged messages.

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